Static Timing Analysis

Project : CE95295
Build Time : 06/29/19 09:10:57
Device : CY8C5888LTI-LP097
Temperature : 0C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz 64.998 MHz
Clock_3 CyMASTER_CLK 50.000 kHz 50.000 kHz 59.372 MHz
clock_1 CyMASTER_CLK 2.000 kHz 2.000 kHz N/A
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 20000ns(50 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ToneQD:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb \ToneQD:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_0 59.372 MHz 16.843 19983.157
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(3,1) 1 \ToneQD:Cnt8:CounterUDB:sC8:counterdp:u0\ \ToneQD:Cnt8:CounterUDB:sC8:counterdp:u0\/clock \ToneQD:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb 1.600
Route 1 \ToneQD:Cnt8:CounterUDB:status_1\ \ToneQD:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb \ToneQD:Cnt8:CounterUDB:reload\/main_1 5.963
macrocell7 U(3,2) 1 \ToneQD:Cnt8:CounterUDB:reload\ \ToneQD:Cnt8:CounterUDB:reload\/main_1 \ToneQD:Cnt8:CounterUDB:reload\/q 2.345
Route 1 \ToneQD:Cnt8:CounterUDB:reload\ \ToneQD:Cnt8:CounterUDB:reload\/q \ToneQD:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.695
datapathcell5 U(3,1) 1 \ToneQD:Cnt8:CounterUDB:sC8:counterdp:u0\ SETUP 4.240
Clock Skew 0.000
\CodeQD:bQuadDec:state_0\/q \CodeQD:Net_1203\/main_5 59.895 MHz 16.696 19983.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell61 U(2,0) 1 \CodeQD:bQuadDec:state_0\ \CodeQD:bQuadDec:state_0\/clock_0 \CodeQD:bQuadDec:state_0\/q 0.875
Route 1 \CodeQD:bQuadDec:state_0\ \CodeQD:bQuadDec:state_0\/q \CodeQD:Net_1203_split\/main_6 8.930
macrocell1 U(0,2) 1 \CodeQD:Net_1203_split\ \CodeQD:Net_1203_split\/main_6 \CodeQD:Net_1203_split\/q 2.345
Route 1 \CodeQD:Net_1203_split\ \CodeQD:Net_1203_split\/q \CodeQD:Net_1203\/main_5 2.089
macrocell57 U(0,2) 1 \CodeQD:Net_1203\ SETUP 2.457
Clock Skew 0.000
\CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb \CodeQD:Cnt8:CounterUDB:sSTSReg:stsreg\/status_3 60.042 MHz 16.655 19983.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(1,2) 1 \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\ \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/clock \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb 1.600
Route 1 \CodeQD:Cnt8:CounterUDB:status_1\ \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb \CodeQD:Cnt8:CounterUDB:status_3\/main_0 10.321
macrocell17 U(2,0) 1 \CodeQD:Cnt8:CounterUDB:status_3\ \CodeQD:Cnt8:CounterUDB:status_3\/main_0 \CodeQD:Cnt8:CounterUDB:status_3\/q 2.345
Route 1 \CodeQD:Cnt8:CounterUDB:status_3\ \CodeQD:Cnt8:CounterUDB:status_3\/q \CodeQD:Cnt8:CounterUDB:sSTSReg:stsreg\/status_3 2.039
statusicell5 U(2,0) 1 \CodeQD:Cnt8:CounterUDB:sSTSReg:stsreg\ SETUP 0.350
Clock Skew 0.000
\CodeQD:bQuadDec:quad_B_filt\/q \CodeQD:Net_1203\/main_5 60.525 MHz 16.522 19983.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(2,4) 1 \CodeQD:bQuadDec:quad_B_filt\ \CodeQD:bQuadDec:quad_B_filt\/clock_0 \CodeQD:bQuadDec:quad_B_filt\/q 0.875
Route 1 \CodeQD:bQuadDec:quad_B_filt\ \CodeQD:bQuadDec:quad_B_filt\/q \CodeQD:Net_1203_split\/main_3 8.756
macrocell1 U(0,2) 1 \CodeQD:Net_1203_split\ \CodeQD:Net_1203_split\/main_3 \CodeQD:Net_1203_split\/q 2.345
Route 1 \CodeQD:Net_1203_split\ \CodeQD:Net_1203_split\/q \CodeQD:Net_1203\/main_5 2.089
macrocell57 U(0,2) 1 \CodeQD:Net_1203\ SETUP 2.457
Clock Skew 0.000
\CodeQD:bQuadDec:quad_A_filt\/q \CodeQD:Net_1251\/main_7 61.774 MHz 16.188 19983.812
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(1,2) 1 \CodeQD:bQuadDec:quad_A_filt\ \CodeQD:bQuadDec:quad_A_filt\/clock_0 \CodeQD:bQuadDec:quad_A_filt\/q 0.875
Route 1 \CodeQD:bQuadDec:quad_A_filt\ \CodeQD:bQuadDec:quad_A_filt\/q \CodeQD:Net_1251_split\/main_2 7.804
macrocell55 U(2,2) 1 \CodeQD:Net_1251_split\ \CodeQD:Net_1251_split\/main_2 \CodeQD:Net_1251_split\/q 2.345
Route 1 \CodeQD:Net_1251_split\ \CodeQD:Net_1251_split\/q \CodeQD:Net_1251\/main_7 2.707
macrocell50 U(2,1) 1 \CodeQD:Net_1251\ SETUP 2.457
Clock Skew 0.000
\ToneQD:bQuadDec:error\/q \ToneQD:Net_1251\/main_7 62.945 MHz 15.887 19984.113
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell47 U(3,3) 1 \ToneQD:bQuadDec:error\ \ToneQD:bQuadDec:error\/clock_0 \ToneQD:bQuadDec:error\/q 0.875
Route 1 \ToneQD:bQuadDec:error\ \ToneQD:bQuadDec:error\/q \ToneQD:Net_1251_split\/main_4 7.509
macrocell35 U(3,1) 1 \ToneQD:Net_1251_split\ \ToneQD:Net_1251_split\/main_4 \ToneQD:Net_1251_split\/q 2.345
Route 1 \ToneQD:Net_1251_split\ \ToneQD:Net_1251_split\/q \ToneQD:Net_1251\/main_7 2.701
macrocell38 U(3,2) 1 \ToneQD:Net_1251\ SETUP 2.457
Clock Skew 0.000
\CodeQD:Net_1260\/q \CodeQD:bQuadDec:Stsreg\/status_2 63.395 MHz 15.774 19984.226
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(1,2) 1 \CodeQD:Net_1260\ \CodeQD:Net_1260\/clock_0 \CodeQD:Net_1260\/q 0.875
Route 1 \CodeQD:Net_1260\ \CodeQD:Net_1260\/q \CodeQD:bQuadDec:Stsreg\/status_2 14.549
statusicell6 U(2,1) 1 \CodeQD:bQuadDec:Stsreg\ SETUP 0.350
Clock Skew 0.000
\CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_0 64.029 MHz 15.618 19984.382
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(1,2) 1 \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\ \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/clock \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb 1.600
Route 1 \CodeQD:Cnt8:CounterUDB:status_1\ \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/z0_comb \CodeQD:Cnt8:CounterUDB:reload\/main_1 5.347
macrocell14 U(1,2) 1 \CodeQD:Cnt8:CounterUDB:reload\ \CodeQD:Cnt8:CounterUDB:reload\/main_1 \CodeQD:Cnt8:CounterUDB:reload\/q 2.345
Route 1 \CodeQD:Cnt8:CounterUDB:reload\ \CodeQD:Cnt8:CounterUDB:reload\/q \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.086
datapathcell6 U(1,2) 1 \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\ SETUP 4.240
Clock Skew 0.000
\CodeQD:bQuadDec:state_1\/q \CodeQD:Net_1251\/main_7 64.131 MHz 15.593 19984.407
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell60 U(0,2) 1 \CodeQD:bQuadDec:state_1\ \CodeQD:bQuadDec:state_1\/clock_0 \CodeQD:bQuadDec:state_1\/q 0.875
Route 1 \CodeQD:bQuadDec:state_1\ \CodeQD:bQuadDec:state_1\/q \CodeQD:Net_1251_split\/main_5 7.209
macrocell55 U(2,2) 1 \CodeQD:Net_1251_split\ \CodeQD:Net_1251_split\/main_5 \CodeQD:Net_1251_split\/q 2.345
Route 1 \CodeQD:Net_1251_split\ \CodeQD:Net_1251_split\/q \CodeQD:Net_1251\/main_7 2.707
macrocell50 U(2,1) 1 \CodeQD:Net_1251\ SETUP 2.457
Clock Skew 0.000
\CodeQD:Net_1260\/q \CodeQD:Net_1251\/main_1 64.168 MHz 15.584 19984.416
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(1,2) 1 \CodeQD:Net_1260\ \CodeQD:Net_1260\/clock_0 \CodeQD:Net_1260\/q 0.875
Route 1 \CodeQD:Net_1260\ \CodeQD:Net_1260\/q \CodeQD:Net_1251\/main_1 12.252
macrocell50 U(2,1) 1 \CodeQD:Net_1251\ SETUP 2.457
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\EEPROM_FF_Reset:Sync:ctrl_reg\/control_0 cy_srff_1/main_1 168.606 MHz 5.931 14.902
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell8 U(3,0) 1 \EEPROM_FF_Reset:Sync:ctrl_reg\ \EEPROM_FF_Reset:Sync:ctrl_reg\/busclk \EEPROM_FF_Reset:Sync:ctrl_reg\/control_0 1.435
Route 1 Net_1889 \EEPROM_FF_Reset:Sync:ctrl_reg\/control_0 cy_srff_1/main_1 2.039
macrocell62 U(3,0) 1 cy_srff_1 SETUP 2.457
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_2X:TimerUDB:timer_enable\/q \Timer_2X:TimerUDB:sT16:timerdp:u1\/ci 64.998 MHz 15.385 5.448
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,4) 1 \Timer_2X:TimerUDB:timer_enable\ \Timer_2X:TimerUDB:timer_enable\/clock_0 \Timer_2X:TimerUDB:timer_enable\/q 0.875
Route 1 \Timer_2X:TimerUDB:timer_enable\ \Timer_2X:TimerUDB:timer_enable\/q \Timer_2X:TimerUDB:trig_reg\/main_1 3.009
macrocell4 U(3,3) 1 \Timer_2X:TimerUDB:trig_reg\ \Timer_2X:TimerUDB:trig_reg\/main_1 \Timer_2X:TimerUDB:trig_reg\/q 2.345
Route 1 \Timer_2X:TimerUDB:trig_reg\ \Timer_2X:TimerUDB:trig_reg\/q \Timer_2X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.606
datapathcell1 U(2,3) 1 \Timer_2X:TimerUDB:sT16:timerdp:u0\ \Timer_2X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_2X:TimerUDB:sT16:timerdp:u0\/co_msb 3.590
Route 1 \Timer_2X:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_2X:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_2X:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(3,3) 1 \Timer_2X:TimerUDB:sT16:timerdp:u1\ SETUP 2.960
Clock Skew 0.000
\Timer_6X:TimerUDB:trig_rise_detected\/q \Timer_6X:TimerUDB:sT16:timerdp:u1\/ci 65.007 MHz 15.383 5.450
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(2,5) 1 \Timer_6X:TimerUDB:trig_rise_detected\ \Timer_6X:TimerUDB:trig_rise_detected\/clock_0 \Timer_6X:TimerUDB:trig_rise_detected\/q 0.875
Route 1 \Timer_6X:TimerUDB:trig_rise_detected\ \Timer_6X:TimerUDB:trig_rise_detected\/q \Timer_6X:TimerUDB:trig_reg\/main_2 2.581
macrocell6 U(2,5) 1 \Timer_6X:TimerUDB:trig_reg\ \Timer_6X:TimerUDB:trig_reg\/main_2 \Timer_6X:TimerUDB:trig_reg\/q 2.345
Route 1 \Timer_6X:TimerUDB:trig_reg\ \Timer_6X:TimerUDB:trig_reg\/q \Timer_6X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.032
datapathcell3 U(3,4) 1 \Timer_6X:TimerUDB:sT16:timerdp:u0\ \Timer_6X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_6X:TimerUDB:sT16:timerdp:u0\/co_msb 3.590
Route 1 \Timer_6X:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_6X:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_6X:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(2,4) 1 \Timer_6X:TimerUDB:sT16:timerdp:u1\ SETUP 2.960
Clock Skew 0.000
\Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_6X:TimerUDB:sT16:timerdp:u1\/ci 65.837 MHz 15.189 5.644
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,5) 1 \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 0.847
Route 1 \Timer_6X:TimerUDB:control_4\ \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_6X:TimerUDB:trig_reg\/main_0 2.415
macrocell6 U(2,5) 1 \Timer_6X:TimerUDB:trig_reg\ \Timer_6X:TimerUDB:trig_reg\/main_0 \Timer_6X:TimerUDB:trig_reg\/q 2.345
Route 1 \Timer_6X:TimerUDB:trig_reg\ \Timer_6X:TimerUDB:trig_reg\/q \Timer_6X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.032
datapathcell3 U(3,4) 1 \Timer_6X:TimerUDB:sT16:timerdp:u0\ \Timer_6X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_6X:TimerUDB:sT16:timerdp:u0\/co_msb 3.590
Route 1 \Timer_6X:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_6X:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_6X:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(2,4) 1 \Timer_6X:TimerUDB:sT16:timerdp:u1\ SETUP 2.960
Clock Skew 0.000
\Timer_6X:TimerUDB:timer_enable\/q \Timer_6X:TimerUDB:sT16:timerdp:u1\/ci 65.902 MHz 15.174 5.659
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(2,5) 1 \Timer_6X:TimerUDB:timer_enable\ \Timer_6X:TimerUDB:timer_enable\/clock_0 \Timer_6X:TimerUDB:timer_enable\/q 0.875
Route 1 \Timer_6X:TimerUDB:timer_enable\ \Timer_6X:TimerUDB:timer_enable\/q \Timer_6X:TimerUDB:trig_reg\/main_1 2.372
macrocell6 U(2,5) 1 \Timer_6X:TimerUDB:trig_reg\ \Timer_6X:TimerUDB:trig_reg\/main_1 \Timer_6X:TimerUDB:trig_reg\/q 2.345
Route 1 \Timer_6X:TimerUDB:trig_reg\ \Timer_6X:TimerUDB:trig_reg\/q \Timer_6X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.032
datapathcell3 U(3,4) 1 \Timer_6X:TimerUDB:sT16:timerdp:u0\ \Timer_6X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_6X:TimerUDB:sT16:timerdp:u0\/co_msb 3.590
Route 1 \Timer_6X:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_6X:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_6X:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(2,4) 1 \Timer_6X:TimerUDB:sT16:timerdp:u1\ SETUP 2.960
Clock Skew 0.000
\Timer_2X:TimerUDB:trig_rise_detected\/q \Timer_2X:TimerUDB:sT16:timerdp:u1\/ci 69.152 MHz 14.461 6.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(3,3) 1 \Timer_2X:TimerUDB:trig_rise_detected\ \Timer_2X:TimerUDB:trig_rise_detected\/clock_0 \Timer_2X:TimerUDB:trig_rise_detected\/q 0.875
Route 1 \Timer_2X:TimerUDB:trig_rise_detected\ \Timer_2X:TimerUDB:trig_rise_detected\/q \Timer_2X:TimerUDB:trig_reg\/main_2 2.085
macrocell4 U(3,3) 1 \Timer_2X:TimerUDB:trig_reg\ \Timer_2X:TimerUDB:trig_reg\/main_2 \Timer_2X:TimerUDB:trig_reg\/q 2.345
Route 1 \Timer_2X:TimerUDB:trig_reg\ \Timer_2X:TimerUDB:trig_reg\/q \Timer_2X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.606
datapathcell1 U(2,3) 1 \Timer_2X:TimerUDB:sT16:timerdp:u0\ \Timer_2X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_2X:TimerUDB:sT16:timerdp:u0\/co_msb 3.590
Route 1 \Timer_2X:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_2X:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_2X:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(3,3) 1 \Timer_2X:TimerUDB:sT16:timerdp:u1\ SETUP 2.960
Clock Skew 0.000
\Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_2X:TimerUDB:sT16:timerdp:u1\/ci 69.175 MHz 14.456 6.377
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,3) 1 \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 0.847
Route 1 \Timer_2X:TimerUDB:control_4\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_2X:TimerUDB:trig_reg\/main_0 2.108
macrocell4 U(3,3) 1 \Timer_2X:TimerUDB:trig_reg\ \Timer_2X:TimerUDB:trig_reg\/main_0 \Timer_2X:TimerUDB:trig_reg\/q 2.345
Route 1 \Timer_2X:TimerUDB:trig_reg\ \Timer_2X:TimerUDB:trig_reg\/q \Timer_2X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.606
datapathcell1 U(2,3) 1 \Timer_2X:TimerUDB:sT16:timerdp:u0\ \Timer_2X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_2X:TimerUDB:sT16:timerdp:u0\/co_msb 3.590
Route 1 \Timer_2X:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_2X:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_2X:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(3,3) 1 \Timer_2X:TimerUDB:sT16:timerdp:u1\ SETUP 2.960
Clock Skew 0.000
\Timer_6X:TimerUDB:sT16:timerdp:u1\/f0_blk_stat_comb \Timer_6X:TimerUDB:timer_enable\/main_0 73.638 MHz 13.580 7.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,4) 1 \Timer_6X:TimerUDB:sT16:timerdp:u1\ \Timer_6X:TimerUDB:sT16:timerdp:u1\/busclk \Timer_6X:TimerUDB:sT16:timerdp:u1\/f0_blk_stat_comb 2.810
Route 1 \Timer_6X:TimerUDB:status_2\ \Timer_6X:TimerUDB:sT16:timerdp:u1\/f0_blk_stat_comb \Timer_6X:TimerUDB:rstSts:stsreg\/status_2 2.709
statusicell2 U(2,5) 1 \Timer_6X:TimerUDB:rstSts:stsreg\ \Timer_6X:TimerUDB:rstSts:stsreg\/status_2 \Timer_6X:TimerUDB:rstSts:stsreg\/interrupt 1.722
Route 1 Net_273 \Timer_6X:TimerUDB:rstSts:stsreg\/interrupt \Timer_6X:TimerUDB:timer_enable\/main_0 3.882
macrocell33 U(2,5) 1 \Timer_6X:TimerUDB:timer_enable\ SETUP 2.457
Clock Skew 0.000
\Timer_6X:TimerUDB:sT16:timerdp:u1\/f0_blk_stat_comb \Timer_6X:TimerUDB:trig_disable\/main_0 73.681 MHz 13.572 7.261
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,4) 1 \Timer_6X:TimerUDB:sT16:timerdp:u1\ \Timer_6X:TimerUDB:sT16:timerdp:u1\/busclk \Timer_6X:TimerUDB:sT16:timerdp:u1\/f0_blk_stat_comb 2.810
Route 1 \Timer_6X:TimerUDB:status_2\ \Timer_6X:TimerUDB:sT16:timerdp:u1\/f0_blk_stat_comb \Timer_6X:TimerUDB:rstSts:stsreg\/status_2 2.709
statusicell2 U(2,5) 1 \Timer_6X:TimerUDB:rstSts:stsreg\ \Timer_6X:TimerUDB:rstSts:stsreg\/status_2 \Timer_6X:TimerUDB:rstSts:stsreg\/interrupt 1.722
Route 1 Net_273 \Timer_6X:TimerUDB:rstSts:stsreg\/interrupt \Timer_6X:TimerUDB:trig_disable\/main_0 3.874
macrocell34 U(2,5) 1 \Timer_6X:TimerUDB:trig_disable\ SETUP 2.457
Clock Skew 0.000
\Timer_2X:TimerUDB:timer_enable\/q \Timer_2X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 76.482 MHz 13.075 7.758
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,4) 1 \Timer_2X:TimerUDB:timer_enable\ \Timer_2X:TimerUDB:timer_enable\/clock_0 \Timer_2X:TimerUDB:timer_enable\/q 0.875
Route 1 \Timer_2X:TimerUDB:timer_enable\ \Timer_2X:TimerUDB:timer_enable\/q \Timer_2X:TimerUDB:trig_reg\/main_1 3.009
macrocell4 U(3,3) 1 \Timer_2X:TimerUDB:trig_reg\ \Timer_2X:TimerUDB:trig_reg\/main_1 \Timer_2X:TimerUDB:trig_reg\/q 2.345
Route 1 \Timer_2X:TimerUDB:trig_reg\ \Timer_2X:TimerUDB:trig_reg\/q \Timer_2X:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.606
datapathcell1 U(2,3) 1 \Timer_2X:TimerUDB:sT16:timerdp:u0\ SETUP 4.240
Clock Skew 0.000
\Timer_2X:TimerUDB:timer_enable\/q \Timer_2X:TimerUDB:sT16:timerdp:u1\/cs_addr_1 76.488 MHz 13.074 7.759
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,4) 1 \Timer_2X:TimerUDB:timer_enable\ \Timer_2X:TimerUDB:timer_enable\/clock_0 \Timer_2X:TimerUDB:timer_enable\/q 0.875
Route 1 \Timer_2X:TimerUDB:timer_enable\ \Timer_2X:TimerUDB:timer_enable\/q \Timer_2X:TimerUDB:trig_reg\/main_1 3.009
macrocell4 U(3,3) 1 \Timer_2X:TimerUDB:trig_reg\ \Timer_2X:TimerUDB:trig_reg\/main_1 \Timer_2X:TimerUDB:trig_reg\/q 2.345
Route 1 \Timer_2X:TimerUDB:trig_reg\ \Timer_2X:TimerUDB:trig_reg\/q \Timer_2X:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.605
datapathcell2 U(3,3) 1 \Timer_2X:TimerUDB:sT16:timerdp:u1\ SETUP 4.240
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\TonePWM:PWMUDB:genblk1:ctrlreg\/control_7 \TonePWM:PWMUDB:runmode_enable\/main_0 2.370
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell9 U(3,1) 1 \TonePWM:PWMUDB:genblk1:ctrlreg\ \TonePWM:PWMUDB:genblk1:ctrlreg\/clock \TonePWM:PWMUDB:genblk1:ctrlreg\/control_7 0.252
Route 1 \TonePWM:PWMUDB:control_7\ \TonePWM:PWMUDB:genblk1:ctrlreg\/control_7 \TonePWM:PWMUDB:runmode_enable\/main_0 2.118
macrocell63 U(3,1) 1 \TonePWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\CodeQD:Net_1251\/q \CodeQD:Net_1251\/main_0 3.266
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell50 U(2,1) 1 \CodeQD:Net_1251\ \CodeQD:Net_1251\/clock_0 \CodeQD:Net_1251\/q 0.875
macrocell50 U(2,1) 1 \CodeQD:Net_1251\ \CodeQD:Net_1251\/q \CodeQD:Net_1251\/main_0 2.391
macrocell50 U(2,1) 1 \CodeQD:Net_1251\ HOLD 0.000
Clock Skew 0.000
\ToneQD:Net_1251\/q \ToneQD:Net_1251\/main_0 3.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(3,2) 1 \ToneQD:Net_1251\ \ToneQD:Net_1251\/clock_0 \ToneQD:Net_1251\/q 0.875
macrocell38 U(3,2) 1 \ToneQD:Net_1251\ \ToneQD:Net_1251\/q \ToneQD:Net_1251\/main_0 2.437
macrocell38 U(3,2) 1 \ToneQD:Net_1251\ HOLD 0.000
Clock Skew 0.000
\TonePWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \TonePWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 3.356
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,5) 1 \TonePWM:PWMUDB:sP8:pwmdp:u0\ \TonePWM:PWMUDB:sP8:pwmdp:u0\/clock \TonePWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 1.270
datapathcell7 U(3,5) 1 \TonePWM:PWMUDB:sP8:pwmdp:u0\ \TonePWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \TonePWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.086
datapathcell7 U(3,5) 1 \TonePWM:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/f0_comb \CodeQD:Net_1276\/main_1 3.394
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(1,2) 1 \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\ \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/clock \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/f0_comb 1.280
Route 1 \CodeQD:Cnt8:CounterUDB:overflow\ \CodeQD:Cnt8:CounterUDB:sC8:counterdp:u0\/f0_comb \CodeQD:Net_1276\/main_1 2.114
macrocell53 U(1,2) 1 \CodeQD:Net_1276\ HOLD 0.000
Clock Skew 0.000
\ToneQD:bQuadDec:state_0\/q \ToneQD:bQuadDec:state_0\/main_5 3.608
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell49 U(3,2) 1 \ToneQD:bQuadDec:state_0\ \ToneQD:bQuadDec:state_0\/clock_0 \ToneQD:bQuadDec:state_0\/q 0.875
macrocell49 U(3,2) 1 \ToneQD:bQuadDec:state_0\ \ToneQD:bQuadDec:state_0\/q \ToneQD:bQuadDec:state_0\/main_5 2.733
macrocell49 U(3,2) 1 \ToneQD:bQuadDec:state_0\ HOLD 0.000
Clock Skew 0.000
\ToneQD:bQuadDec:state_0\/q \ToneQD:Net_1203\/main_4 3.760
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell49 U(3,2) 1 \ToneQD:bQuadDec:state_0\ \ToneQD:bQuadDec:state_0\/clock_0 \ToneQD:bQuadDec:state_0\/q 0.875
Route 1 \ToneQD:bQuadDec:state_0\ \ToneQD:bQuadDec:state_0\/q \ToneQD:Net_1203\/main_4 2.885
macrocell45 U(2,2) 1 \ToneQD:Net_1203\ HOLD 0.000
Clock Skew 0.000
\ToneQD:bQuadDec:state_0\/q \ToneQD:Net_1260\/main_3 3.760
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell49 U(3,2) 1 \ToneQD:bQuadDec:state_0\ \ToneQD:bQuadDec:state_0\/clock_0 \ToneQD:bQuadDec:state_0\/q 0.875
Route 1 \ToneQD:bQuadDec:state_0\ \ToneQD:bQuadDec:state_0\/q \ToneQD:Net_1260\/main_3 2.885
macrocell46 U(2,2) 1 \ToneQD:Net_1260\ HOLD 0.000
Clock Skew 0.000
\CodeQD:Net_1203\/q \CodeQD:Cnt8:CounterUDB:count_stored_i\/main_0 3.764
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell57 U(0,2) 1 \CodeQD:Net_1203\ \CodeQD:Net_1203\/clock_0 \CodeQD:Net_1203\/q 0.875
Route 1 \CodeQD:Net_1203\ \CodeQD:Net_1203\/q \CodeQD:Cnt8:CounterUDB:count_stored_i\/main_0 2.889
macrocell56 U(1,2) 1 \CodeQD:Cnt8:CounterUDB:count_stored_i\ HOLD 0.000
Clock Skew 0.000
\ToneQD:bQuadDec:state_0\/q \ToneQD:Net_1251\/main_6 3.765
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell49 U(3,2) 1 \ToneQD:bQuadDec:state_0\ \ToneQD:bQuadDec:state_0\/clock_0 \ToneQD:bQuadDec:state_0\/q 0.875
Route 1 \ToneQD:bQuadDec:state_0\ \ToneQD:bQuadDec:state_0\/q \ToneQD:Net_1251\/main_6 2.890
macrocell38 U(3,2) 1 \ToneQD:Net_1251\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\EEPROM_FF_Reset:Sync:ctrl_reg\/control_0 cy_srff_1/main_1 2.473
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell8 U(3,0) 1 \EEPROM_FF_Reset:Sync:ctrl_reg\ \EEPROM_FF_Reset:Sync:ctrl_reg\/busclk \EEPROM_FF_Reset:Sync:ctrl_reg\/control_0 0.434
Route 1 Net_1889 \EEPROM_FF_Reset:Sync:ctrl_reg\/control_0 cy_srff_1/main_1 2.039
macrocell62 U(3,0) 1 cy_srff_1 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer_2X:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_2X:TimerUDB:sT16:timerdp:u1\/ci 1.500
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,3) 1 \Timer_2X:TimerUDB:sT16:timerdp:u0\ \Timer_2X:TimerUDB:sT16:timerdp:u0\/clock \Timer_2X:TimerUDB:sT16:timerdp:u0\/co_msb 1.500
Route 1 \Timer_2X:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_2X:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_2X:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(3,3) 1 \Timer_2X:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_6X:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_6X:TimerUDB:sT16:timerdp:u1\/ci 1.500
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,4) 1 \Timer_6X:TimerUDB:sT16:timerdp:u0\ \Timer_6X:TimerUDB:sT16:timerdp:u0\/clock \Timer_6X:TimerUDB:sT16:timerdp:u0\/co_msb 1.500
Route 1 \Timer_6X:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_6X:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_6X:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(2,4) 1 \Timer_6X:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_2X:TimerUDB:run_mode\/main_0 2.356
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,3) 1 \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.252
Route 1 \Timer_2X:TimerUDB:control_7\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_2X:TimerUDB:run_mode\/main_0 2.104
macrocell26 U(3,3) 1 \Timer_2X:TimerUDB:run_mode\ HOLD 0.000
Clock Skew 0.000
\Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_2X:TimerUDB:trig_rise_detected\/main_1 2.356
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,3) 1 \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.252
Route 1 \Timer_2X:TimerUDB:control_7\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_2X:TimerUDB:trig_rise_detected\/main_1 2.104
macrocell30 U(3,3) 1 \Timer_2X:TimerUDB:trig_rise_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_2X:TimerUDB:trig_fall_detected\/main_1 2.356
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,3) 1 \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.252
Route 1 \Timer_2X:TimerUDB:control_7\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_2X:TimerUDB:trig_fall_detected\/main_1 2.104
macrocell31 U(3,3) 1 \Timer_2X:TimerUDB:trig_fall_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_2X:TimerUDB:trig_rise_detected\/main_2 2.360
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,3) 1 \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 0.252
Route 1 \Timer_2X:TimerUDB:control_4\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_2X:TimerUDB:trig_rise_detected\/main_2 2.108
macrocell30 U(3,3) 1 \Timer_2X:TimerUDB:trig_rise_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_2X:TimerUDB:trig_fall_detected\/main_2 2.360
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,3) 1 \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 0.252
Route 1 \Timer_2X:TimerUDB:control_4\ \Timer_2X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_2X:TimerUDB:trig_fall_detected\/main_2 2.108
macrocell31 U(3,3) 1 \Timer_2X:TimerUDB:trig_fall_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_6X:TimerUDB:trig_disable\/main_2 2.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,5) 1 \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 0.252
Route 1 \Timer_6X:TimerUDB:control_4\ \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_6X:TimerUDB:trig_disable\/main_2 2.406
macrocell34 U(2,5) 1 \Timer_6X:TimerUDB:trig_disable\ HOLD 0.000
Clock Skew 0.000
\Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_6X:TimerUDB:trig_rise_detected\/main_4 2.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,5) 1 \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 0.252
Route 1 \Timer_6X:TimerUDB:control_4\ \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_6X:TimerUDB:trig_rise_detected\/main_4 2.406
macrocell36 U(2,5) 1 \Timer_6X:TimerUDB:trig_rise_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_6X:TimerUDB:trig_fall_detected\/main_4 2.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,5) 1 \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 0.252
Route 1 \Timer_6X:TimerUDB:control_4\ \Timer_6X:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_6X:TimerUDB:trig_fall_detected\/main_4 2.406
macrocell37 U(2,5) 1 \Timer_6X:TimerUDB:trig_fall_detected\ HOLD 0.000
Clock Skew 0.000
+ Input To Output Section
Source Destination Delay (ns)
PWM_On(0)_PAD PWM_Out(0)_PAD 33.846
Type Location Fanout Instance/Net Source Dest Delay (ns)
CE95295 1 PWM_On(0)_PAD PWM_On(0)_PAD PWM_On(0)_PAD 0.000
Route 1 PWM_On(0)_PAD PWM_On(0)_PAD PWM_On(0)/pad_in 0.000
iocell24 P3[1] 1 PWM_On(0) PWM_On(0)/pad_in PWM_On(0)/fb 6.259
Route 1 Net_1679 PWM_On(0)/fb Net_1597/main_1 4.381
macrocell2 U(3,0) 1 Net_1597 Net_1597/main_1 Net_1597/q 2.345
Route 1 Net_1597 Net_1597/q PWM_Out(0)/pin_input 6.241
iocell19 P3[0] 1 PWM_Out(0) PWM_Out(0)/pin_input PWM_Out(0)/pad_out 14.620
Route 1 PWM_Out(0)_PAD PWM_Out(0)/pad_out PWM_Out(0)_PAD 0.000
+ Input To Clock Section
+ Clock_3
Source Destination Delay (ns)
Config_SwitchB(0)_PAD \ToneQD:bQuadDec:quad_A_filt\/main_1 20.742
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Config_SwitchB(0)_PAD Config_SwitchB(0)_PAD Config_SwitchB(0)/pad_in 0.000
iocell22 P3[4] 1 Config_SwitchB(0) Config_SwitchB(0)/pad_in Config_SwitchB(0)/fb 6.038
Route 1 Net_799 Config_SwitchB(0)/fb \ToneQD:bQuadDec:quad_A_filt\/main_1 12.247
macrocell21 U(3,4) 1 \ToneQD:bQuadDec:quad_A_filt\ SETUP 2.457
Clock Clock path delay 0.000
Code_B_Input(0)_PAD \CodeQD:bQuadDec:quad_B_filt\/main_1 16.412
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Code_B_Input(0)_PAD Code_B_Input(0)_PAD Code_B_Input(0)/pad_in 0.000
iocell21 P15[5] 1 Code_B_Input(0) Code_B_Input(0)/pad_in Code_B_Input(0)/fb 7.061
Route 1 Net_99 Code_B_Input(0)/fb \CodeQD:bQuadDec:quad_B_filt\/main_1 6.894
macrocell24 U(2,4) 1 \CodeQD:bQuadDec:quad_B_filt\ SETUP 2.457
Clock Clock path delay 0.000
Tone_A_Input(0)_PAD \ToneQD:bQuadDec:quad_A_filt\/main_0 16.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Tone_A_Input(0)_PAD Tone_A_Input(0)_PAD Tone_A_Input(0)/pad_in 0.000
iocell13 P15[3] 1 Tone_A_Input(0) Tone_A_Input(0)/pad_in Tone_A_Input(0)/fb 6.523
Route 1 Net_230 Tone_A_Input(0)/fb \ToneQD:bQuadDec:quad_A_filt\/main_0 7.365
macrocell21 U(3,4) 1 \ToneQD:bQuadDec:quad_A_filt\ SETUP 2.457
Clock Clock path delay 0.000
Code_A_Input(0)_PAD \CodeQD:bQuadDec:quad_A_filt\/main_1 15.012
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Code_A_Input(0)_PAD Code_A_Input(0)_PAD Code_A_Input(0)/pad_in 0.000
iocell20 P15[4] 1 Code_A_Input(0) Code_A_Input(0)/pad_in Code_A_Input(0)/fb 7.473
Route 1 Net_351 Code_A_Input(0)/fb \CodeQD:bQuadDec:quad_A_filt\/main_1 5.082
macrocell23 U(1,2) 1 \CodeQD:bQuadDec:quad_A_filt\ SETUP 2.457
Clock Clock path delay 0.000
Tone_B_Input(0)_PAD \ToneQD:bQuadDec:quad_B_filt\/main_0 14.496
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Tone_B_Input(0)_PAD Tone_B_Input(0)_PAD Tone_B_Input(0)/pad_in 0.000
iocell12 P15[2] 1 Tone_B_Input(0) Tone_B_Input(0)/pad_in Tone_B_Input(0)/fb 6.653
Route 1 Net_34 Tone_B_Input(0)/fb \ToneQD:bQuadDec:quad_B_filt\/main_0 5.386
macrocell22 U(2,1) 1 \ToneQD:bQuadDec:quad_B_filt\ SETUP 2.457
Clock Clock path delay 0.000
Save_B(0)_PAD cy_srff_1/main_2 14.095
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Save_B(0)_PAD Save_B(0)_PAD Save_B(0)/pad_in 0.000
iocell23 P3[2] 1 Save_B(0) Save_B(0)/pad_in Save_B(0)/fb 6.250
Route 1 Net_922 Save_B(0)/fb cy_srff_1/main_2 5.388
macrocell62 U(3,0) 1 cy_srff_1 SETUP 2.457
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_3
Source Destination Delay (ns)
Net_1595/q PWM_Out(0)_PAD 26.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell64 U(3,0) 1 Net_1595 Net_1595/clock_0 Net_1595/q 0.875
Route 1 Net_1595 Net_1595/q Net_1597/main_0 2.020
macrocell2 U(3,0) 1 Net_1597 Net_1597/main_0 Net_1597/q 2.345
Route 1 Net_1597 Net_1597/q PWM_Out(0)/pin_input 6.241
iocell19 P3[0] 1 PWM_Out(0) PWM_Out(0)/pin_input PWM_Out(0)/pad_out 14.620
Route 1 PWM_Out(0)_PAD PWM_Out(0)/pad_out PWM_Out(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
\LED_Register:Sync:ctrl_reg\/control_2 Pin_3(0)_PAD 24.524
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED_Register:Sync:ctrl_reg\ \LED_Register:Sync:ctrl_reg\/busclk \LED_Register:Sync:ctrl_reg\/control_2 1.435
Route 1 Net_194 \LED_Register:Sync:ctrl_reg\/control_2 Pin_3(0)/pin_input 7.302
iocell6 P2[2] 1 Pin_3(0) Pin_3(0)/pin_input Pin_3(0)/pad_out 15.787
Route 1 Pin_3(0)_PAD Pin_3(0)/pad_out Pin_3(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Register:Sync:ctrl_reg\/control_1 Pin_2(0)_PAD 24.437
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED_Register:Sync:ctrl_reg\ \LED_Register:Sync:ctrl_reg\/busclk \LED_Register:Sync:ctrl_reg\/control_1 1.435
Route 1 Net_193 \LED_Register:Sync:ctrl_reg\/control_1 Pin_2(0)/pin_input 7.111
iocell5 P2[1] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 15.891
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Register:Sync:ctrl_reg\/control_0 Pin_1(0)_PAD 24.286
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED_Register:Sync:ctrl_reg\ \LED_Register:Sync:ctrl_reg\/busclk \LED_Register:Sync:ctrl_reg\/control_0 1.435
Route 1 Net_192 \LED_Register:Sync:ctrl_reg\/control_0 Pin_1(0)/pin_input 7.184
iocell4 P2[0] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.667
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Register:Sync:ctrl_reg\/control_5 Pin_6(0)_PAD 24.207
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED_Register:Sync:ctrl_reg\ \LED_Register:Sync:ctrl_reg\/busclk \LED_Register:Sync:ctrl_reg\/control_5 1.435
Route 1 Net_197 \LED_Register:Sync:ctrl_reg\/control_5 Pin_6(0)/pin_input 7.119
iocell9 P2[5] 1 Pin_6(0) Pin_6(0)/pin_input Pin_6(0)/pad_out 15.653
Route 1 Pin_6(0)_PAD Pin_6(0)/pad_out Pin_6(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Register:Sync:ctrl_reg\/control_3 Pin_4(0)_PAD 23.999
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED_Register:Sync:ctrl_reg\ \LED_Register:Sync:ctrl_reg\/busclk \LED_Register:Sync:ctrl_reg\/control_3 1.435
Route 1 Net_195 \LED_Register:Sync:ctrl_reg\/control_3 Pin_4(0)/pin_input 7.127
iocell7 P2[3] 1 Pin_4(0) Pin_4(0)/pin_input Pin_4(0)/pad_out 15.437
Route 1 Pin_4(0)_PAD Pin_4(0)/pad_out Pin_4(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Register:Sync:ctrl_reg\/control_4 Pin_5(0)_PAD 23.993
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED_Register:Sync:ctrl_reg\ \LED_Register:Sync:ctrl_reg\/busclk \LED_Register:Sync:ctrl_reg\/control_4 1.435
Route 1 Net_196 \LED_Register:Sync:ctrl_reg\/control_4 Pin_5(0)/pin_input 7.209
iocell8 P2[4] 1 Pin_5(0) Pin_5(0)/pin_input Pin_5(0)/pad_out 15.349
Route 1 Pin_5(0)_PAD Pin_5(0)/pad_out Pin_5(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Register:Sync:ctrl_reg\/control_6 Pin_7(0)_PAD 23.751
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED_Register:Sync:ctrl_reg\ \LED_Register:Sync:ctrl_reg\/busclk \LED_Register:Sync:ctrl_reg\/control_6 1.435
Route 1 Net_198 \LED_Register:Sync:ctrl_reg\/control_6 Pin_7(0)/pin_input 7.192
iocell10 P2[6] 1 Pin_7(0) Pin_7(0)/pin_input Pin_7(0)/pad_out 15.124
Route 1 Pin_7(0)_PAD Pin_7(0)/pad_out Pin_7(0)_PAD 0.000
Clock Clock path delay 0.000
\LED_Register:Sync:ctrl_reg\/control_7 Pin_8(0)_PAD 23.452
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED_Register:Sync:ctrl_reg\ \LED_Register:Sync:ctrl_reg\/busclk \LED_Register:Sync:ctrl_reg\/control_7 1.435
Route 1 Net_199 \LED_Register:Sync:ctrl_reg\/control_7 Pin_8(0)/pin_input 7.143
iocell11 P2[7] 1 Pin_8(0) Pin_8(0)/pin_input Pin_8(0)/pad_out 14.874
Route 1 Pin_8(0)_PAD Pin_8(0)/pad_out Pin_8(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 20000ns(50 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\CodeQD:Net_1260\/q \CodeQD:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 75.552 MHz 13.236 19986.764
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(1,2) 1 \CodeQD:Net_1260\ \CodeQD:Net_1260\/clock_0 \CodeQD:Net_1260\/q 0.875
Route 1 \CodeQD:Net_1260\ \CodeQD:Net_1260\/q \CodeQD:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 12.361
statusicell5 U(2,0) 1 \CodeQD:Cnt8:CounterUDB:sSTSReg:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\ToneQD:Net_1260\/q \ToneQD:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 125.125 MHz 7.992 19992.008
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell46 U(2,2) 1 \ToneQD:Net_1260\ \ToneQD:Net_1260\/clock_0 \ToneQD:Net_1260\/q 0.875
Route 1 \ToneQD:Net_1260\ \ToneQD:Net_1260\/q \ToneQD:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 7.117
statusicell3 U(3,4) 1 \ToneQD:Cnt8:CounterUDB:sSTSReg:stsreg\ RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timers_RST:Sync:ctrl_reg\/control_0 \Timer_6X:TimerUDB:rstSts:stsreg\/reset 154.703 MHz 6.464 14.369
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Timers_RST:Sync:ctrl_reg\ \Timers_RST:Sync:ctrl_reg\/busclk \Timers_RST:Sync:ctrl_reg\/control_0 1.435
Route 1 Net_113 \Timers_RST:Sync:ctrl_reg\/control_0 \Timer_6X:TimerUDB:rstSts:stsreg\/reset 5.029
statusicell2 U(2,5) 1 \Timer_6X:TimerUDB:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
\Timers_RST:Sync:ctrl_reg\/control_0 \Timer_2X:TimerUDB:rstSts:stsreg\/reset 159.439 MHz 6.272 14.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Timers_RST:Sync:ctrl_reg\ \Timers_RST:Sync:ctrl_reg\/busclk \Timers_RST:Sync:ctrl_reg\/control_0 1.435
Route 1 Net_113 \Timers_RST:Sync:ctrl_reg\/control_0 \Timer_2X:TimerUDB:rstSts:stsreg\/reset 4.837
statusicell1 U(3,3) 1 \Timer_2X:TimerUDB:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\ToneQD:Net_1260\/q \ToneQD:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 7.992
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell46 U(2,2) 1 \ToneQD:Net_1260\ \ToneQD:Net_1260\/clock_0 \ToneQD:Net_1260\/q 0.875
Route 1 \ToneQD:Net_1260\ \ToneQD:Net_1260\/q \ToneQD:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 7.117
statusicell3 U(3,4) 1 \ToneQD:Cnt8:CounterUDB:sSTSReg:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\CodeQD:Net_1260\/q \CodeQD:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 13.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(1,2) 1 \CodeQD:Net_1260\ \CodeQD:Net_1260\/clock_0 \CodeQD:Net_1260\/q 0.875
Route 1 \CodeQD:Net_1260\ \CodeQD:Net_1260\/q \CodeQD:Cnt8:CounterUDB:sSTSReg:stsreg\/reset 12.361
statusicell5 U(2,0) 1 \CodeQD:Cnt8:CounterUDB:sSTSReg:stsreg\ REMOVAL 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timers_RST:Sync:ctrl_reg\/control_0 \Timer_2X:TimerUDB:rstSts:stsreg\/reset 5.271
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Timers_RST:Sync:ctrl_reg\ \Timers_RST:Sync:ctrl_reg\/busclk \Timers_RST:Sync:ctrl_reg\/control_0 0.434
Route 1 Net_113 \Timers_RST:Sync:ctrl_reg\/control_0 \Timer_2X:TimerUDB:rstSts:stsreg\/reset 4.837
statusicell1 U(3,3) 1 \Timer_2X:TimerUDB:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\Timers_RST:Sync:ctrl_reg\/control_0 \Timer_6X:TimerUDB:rstSts:stsreg\/reset 5.463
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,2) 1 \Timers_RST:Sync:ctrl_reg\ \Timers_RST:Sync:ctrl_reg\/busclk \Timers_RST:Sync:ctrl_reg\/control_0 0.434
Route 1 Net_113 \Timers_RST:Sync:ctrl_reg\/control_0 \Timer_6X:TimerUDB:rstSts:stsreg\/reset 5.029
statusicell2 U(2,5) 1 \Timer_6X:TimerUDB:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000